1. Field of the Invention
The present invention relates to a phase difference detection circuit, a phase difference detecting method, an optical disk drive, and an optical disk drive controlling method.
2. Description of Related Art
Nowadays, optical disks such as CD (compact disc) and DVD (digital versatile disc) have been widely available. In addition, new optical disks have been under development. Optical disk drives that read/write information from/to the optical disk amplify and shape signals read through light pick-up to supply read data to a PLL (phase locked loop) circuit. The PLL circuit generates a read clock synchronized with the read data. The read data is extracted in accordance with the synchronized read clock and subjected to signal processing to obtain final reproduction data.
At this time, attention should be paid to the fact that data read from the disk involves fluctuation in the time axis direction called “jitter”. The jitter is caused by a reading device inclined with respect to a reading surface of the disk, that is, the optical axis of a reproducing laser beam not vertical to the disk surface, or the laser power inadequate for writing data. In some cases, correct signals cannot be input, leading to an error in reading data or correct data cannot be obtained due to the jitter.
Further, a read clock that is generated based on the read data with the jitter involves the jitter. In this case, an important problem is not the jitter in both the read data and the read clock but a relative phase difference. In such a case, even if the jitter of the read data is only detected without considering the jitter of the read clock, the detected jitter is different from a relative phase difference as a practical problem.
To that end, a method of detecting a jitter has been under study, and there have been some proposals. As the method of detecting the jitter, there has been proposed a method of inputting a read clock signal the rising/falling edge of which appears concurrently with that of the read data signal and detecting a delay therebetween with a counter (see Japanese Unexamined Patent Publication No. 2001-273715 (Kobayashi), for instance).
The related art disclosed in Kobayashi is discussed in brief. FIG. 10 shows the structure of a jitter detecting device of the related art. The jitter detecting device of the related art generates a read clock of which the edge is synchronous with that of the input read data by means of a PLL circuit 30, and a phase difference between the read data and the read clock is detected with a phase difference detection circuit 32.
The phase differential signal detected by the phase difference detection circuit 32 is output to a Schmitt circuit 33. The Schmitt circuit 33 compares the received phase difference with a threshold value preset by a threshold setting register 31, and sends, if the received phase difference exceeds the threshold value, this comparison result to a counter 34. The counter 34 increments a count value by 1 when the phase difference exceeds the threshold value.
The count value of the counter 34 is recorded in a register 35. The recorded value is output to a CPU through a CPU interface as needed. It is thus possible to count the number of times the phase difference exceeds the present threshold value.
With this method, however, the circuit is operated with reference to the edge of the read data signal, a delay of the read clock signal can be detected but the jitter of the advanced read clock signal cannot be detected. Further, the method only counts the number of times the threshold value is exceeded, thus it is impossible to evaluate the phase difference deviation of the rising edge and falling edge of the read data signal. It is still another problem that the jitter cannot be detected in consideration of the jitter of the read clock signal itself.
As mentioned above, the jitter detecting method using the conventional phase difference detection circuit is incapable of detecting the jitter of the advanced read clock signal. As another problem thereof, the jitter cannot be relatively detected in consideration of the influence of the jitter in the read clock signal itself.